Many electronic circuits, such as processor chips, have one or more pads for input and/or output (I/O) of data and/or other signals between the circuit and other devices. In the case of a processor, the processor is often printed on a silicon die, and the die is placed in a package. The pads of the processor are coupled to corresponding pins on the package. The pad capacitance is a parameter usable for evaluating I/O performance. Currently, pad capacitance is measured using a time-domain reflectometry (TDR) method after the circuit is printed on silicon. In the TDR method, a signal is sent through a pin and the reflected signal is evaluated. However, the TDR method requires the circuit to be turned off and is limited to measuring the pad capacitance under one set of process, voltage and temperature (PVT) conditions (e.g., in one PVT corner). Furthermore, the test process is time consuming, and is therefore only performed on a few units of a batch of circuits. Accordingly, the pad capacitance data that is collected is limited and contains substantial margin for error. Additionally, the data is measured at the pin, and package traces can introduce additional error.